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r8c/12 group single-chip 16-bit cmos microcomputer rej03b0068-0010z rev.0.10 2003.10.28 rev.0.10 oct 28, 2003 page 1 of 25 1. overview this mcu is built using the high-performance silicon gate cmos process using a r8c tiny series cpu core and is packaged in a 32-pin plastic molded lqfp. this mcu operates using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, it is capable of executing instructions at high speed. the data flash rom (2 kb x 2 blocks) is embedded. 1.1 applications electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
rev.0.10 oct 28, 2003 page 2 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview table 1.1 performance outline 1.2 performance outline table 1.1. lists the performance outline of this mcu. item performance cpu number of basic instructions 89 instructions shortest instruction execution time 62.5 ns (f(x in ) = 16 mh z , v cc = 3.0 to 5.5 v) 100 ns (f(x in ) = 10 mh z , v cc = 2.7 to 5.5 v) operating mode single-chip address space 1m bytes memory capacity see table 1.2 ?roduct list peripheral interrupt internal: 10 sources, external: 5 sources, function software: 4 sources, priority level: 7 levels watchdog timer 15 bits x 1 (with prescaler) reset start function selectable timer timer x: 8 bits x 1 channel, timer y: 8 bits x 1 channel, timer z: 8 bits x 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits x 1 channel input capture circuit serial i/o ? channel clock synchronous, uart ? channel uart a-d converter 10-bit a-d converter: 1 circuit, 8 channels clock generation circuit 2 circuits ?ain clock generation circuit (equipped with a built-in feedback resistor) ?ing oscillator oscillation stop detection function stop detection of main clock oscillation port input/output: 22 (including led drive port), input: 2 (led drive i/o port: 8, max. 20 ma) electrical power supply voltage v cc = 3.0 to 5.5 v (f(x in ) = 16 mh z ) characteristics v cc = 2.7 to 5.5 v (f(x in ) = 10 mh z ) power consumption typ. 8 ma (v cc = 5.0 v, (f(x in ) = 16 mh z , high-speed mode) typ. 5 ma (v cc = 3.0 v, (f(x in ) = 10 mh z , high-speed mode) tbd (v cc = 3.0 v, wait mode) typ. 0.7 a (v cc = 3.0 v, stop mode) flash memory program/erase voltage v cc = 2.7 to 5.5 v number of program/erase 10000 times (data area) 100 times (program area) operating ambient temperature -20 to 85 ? -40 to 85 ? (option) package 32-pin plastic mold lqfp if you require this option, please specify so.
rev.0.10 oct 28, 2003 page 3 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview 1.3 block diagram figure 1.1. shows this mcu block diagram. figure 1.1 block diagram t i m e r x ( 8 b i t s ) t i m e r y ( 8 b i t s ) t i m e r z ( 8 b i t s ) t i m e r c ( 1 6 b i t s ) watchdog timer (15 bits) m e m o r y r o m ( n o t e 1 ) r8c series cpu core i / o p o r t p o r t p 0 8 p o r t p 1 8 p o r t p 3 5 multiplier system clock generator x in -x out ring oscillator uart (8 bits ? 1 channel) port p4 1 2 pe r i p h e r a l f u n c t i o n s uart or clock synchronous serial i/o (8 bits ? 1 channel) a-d converter (10 bits ? 8 channels) r a m ( n o t e 2 ) note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. r0l r0h r 1 hr1l r2 r3 a 0 a 1 fb sb isp usp intb pc f l g t i m e r
rev.0.10 oct 28, 2003 page 4 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview package type: fp : 32p6u rom capacity: 2 : 8 kbytes. 3 : 12 kbytes. 4 : 16 kbytes. memory type: f: flash memory version type no. r 5 f 21 12 4 d fp r8c/12 group r8c/tiny series shows characteristics and others. d: operating ambient temperature 40 c to 85 c no symbol: operating ambient temperature 20 c to 85 c renesas mcu renesas semiconductors 1.4 product information table 1.2 lists the products. table 1.2 product list figure 1.2 type no., memory size, and package r a m c a p a c i t y rom capacity p a c k a g e t y p er e m a r k s t y p e n o . as of october 2003 f l a s h m e m o r y v e r s i o n r 5 f 2 1 1 2 2 f p 3 2p 6 u - a 8 k b y t e s 512 bytes : u n d e r d e v e l o p m e n t * * * * 3 2p 6 u - a 12k bytes 7 6 8 b y t e s * * 3 2p 6 u - a 1 6 k b y t e s1 k b y t e s * * r 5 f 2 1 1 2 3f p r 5 f 2 1 1 2 4 f p r5f21122dfp 32p6u-a 8k bytes 512 bytes ** 32p6u-a 12k bytes 768 bytes * * 3 2p 6 u - a 16k bytes 1 k b y t e s * * r5f21123dfp r5f21124dfp d version p r o g r a m a r e ad a t a a r e a 2 k b y t e s x 2 2 k b y t e s x 2 2 k b y t e s x 2 2k bytes x 2 2k bytes x 2 2k bytes x 2
rev.0.10 oct 28, 2003 page 5 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview package: 32p6u-a figure 1.3 pin configuration (top view) pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r 8 c / 1 2 g r o u p x i n / p 4 6 x o u t / p 4 7 ( n o t e 1 ) v s s r e s e t v c c c n v s s p 1 7 / i n t 1 / c n t r 0 p 1 6 / c l k 0 p 1 5 / r x d 0 p1 4 /txd 0 p 3 7 / t x d 1 0 / r x d 1 p 3 0 / c n t r 0 p 3 3 / i n t 3 / t c i n p 3 1 / t z o u t p 3 2 / i n t 2 / c n t r 1 i v c c a v s s a v c c / v r e f p0 3 /an 4 p0 2 /an 5 p0 1 /an 6 p0 0 /an 7 /txd 11 p 0 6 / a n 1 p0 5 /an 2 p 0 4 / a n 3 p 4 5 / i n t 0 p 1 0 / k i 0 p 1 1 / k i 1 p 1 2 / k i 2 p 1 3 / k i 3 p 0 7 / a n 0 m o d e note 1: p4 7 functions only as an input port. 2: when using on-chip debugger, do not use pins p0 0 /an 7 /txd 11 and p3 7 /txd 10 /rxd 1 . 1.5 pin configuration figure 1.3 shows the pin configuration (top view).
rev.0.10 oct 28, 2003 page 6 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview signal name pin name i/o type power supply vcc, input input vss ivcc ivcc output analog power avcc, input supply input avss reset input ___________ reset input cnvss cnvss input mode mode input main clock input x in input main clock output x out output _____ int interrupt input _______ _______ int 0 to int 3 input key input interrupt _____ _____ ki 0 to ki 3 input input timer x cntr 0 input/output __________ cntr 0 output timer y cntr 1 input/output timer z tz out output timer c tc in input serial interface clk 0 input/output rxd 0 , rxd 1 input txd 0 , txd 10 , output txd 11 reference voltage v ref input input a-d converter an 0 to an 7 input i/o port p0 0 to p0 7 , input/output p1 0 to p1 7 , p3 0 to p3 3 , p3 7 , p4 5 input port p4 6 , p4 7 input function apply 2.7 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. connect this pin to vss via a capacitor. these are power supply input pins for a-d converter. con- nect the avcc pin to vcc. connect the avss pin to vss. ??on this input resets the mcu. connect this pin to vss via a resistor. connect this pin to vcc via a resistor. these pins are provided for the main clock generat- ing circuit input/output. connect a ceramic resonator or a crystal oscillator between the x in and x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. ______ these are int interrupt input pins. these are key input interrupt input pins. this is the timer x i/o pin. this is the timer x output pin. this is the timer y i/o pin. this is the timer z output pin. this is the timer c input pin. this is a transfer clock i/o pin. these are serial data input pins. these are serial data output pins. this is a reference voltage input pin for a-d con- verter. connect the v ref pin to vcc. these are analog input pins for a-d converter. these are 8-bit cmos i/o ports. each port has an input/output select direction register, allowing each pin in that port to be directed for input or output indi- vidually. any port set to input can select whether to use a pull- up resistor or not by program. p1 0 to p1 7 also function as led drive ports. these are input only pins. 1.6 pin description table 1.3 shows the pin description table 1.3 pin description
rev.0.10 oct 28, 2003 page 7 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processing unit (cpu) 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data regis- ters. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. data registers (note 1) address registers (note 1) frame base registers (note 1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note 1: these re g isters com p rise a re g ister bank. there are two re g ister banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa aa aa aa aa aa aa aaaaaa aaaaaa aa aa a a aa aa aa aa aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl. figure 2.1 central processing unit register
rev.0.10 oct 28, 2003 page 8 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processing unit (cpu) 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and logic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to ?? 2.8.3 zero flag (z flag) this flag is set to ??when an arithmetic operation resulted in 0; otherwise, it is ?? 2.8.4 sign flag (s flag) this flag is set to ??when an arithmetic operation resulted in a negative value; otherwise, it is ?? 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is ??; register bank 1 is selected when this flag is ?? 2.8.6 overflow flag (o flag) this flag is set to ??when the operation resulted in an overflow; otherwise, it is ?? 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is ?? and are enabled when the i flag is ?? the i flag is cleared to ??when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is ?? usp is selected when the u flag is ?? the u flag is cleared to ??when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate.
rev.0.10 oct 05, 2003 page 9 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 3. memory 3. memory figure 3.1 is a memory map of this mcu. the address space extends the 1m bytes from address 00000 16 to fffff 16 . the internal rom (program area) is allocated in a lower address direction beginning with address 0ffff 16 . for example, a 16-kbyte internal rom is allocated to the addresses from 0c000 16 to 0ffff 16 . the fixed interrupt vector table is allocated to the addresses from 0ffdc 16 to 0ffff 16 . therefore, store the start address of each interrupt routine here. the internal rom (data area) is allocated to the addresses from 02000 16 to 02fff 16 . the internal ram is allocated in an upper address direction beginning with address 00400 16 . for ex- ample, a 1-kbyte internal ram is allocated to the addresses from 00400 16 to 007ff 16 . in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. special function registers (sfr) are allocated to the addresses from 00000 16 to 002ff 16 . peripheral function control registers are located here. of the sfr, any space which has no functions allocated is reserved for future use and cannot be used by users. figure 3.1 memory map 00000 16 0yyyy 16 0ffff 16 002ff 16 00400 16 internal rom (program area) sfr (see chapter 4 for details.) 0ffdc 16 0ffff 16 undefined instruction overflow brk instruction address match single step watchdog timer?scillation stop detection reset (reserved) type name 0xxxx 16 internal ram fffff 16 address 0xxxx 16 005ff 16 internal ram size 007ff 16 512 bytes 1k bytes 006ff 16 768 bytes address 0yyyy 16 0e000 16 internal rom size 0c000 16 8k bytes 16k bytes 0d000 16 12k bytes expanding area (reserved) r5f21124fp, r5f21124dfp r5f21123fp, r5f21123dfp r5f21122fp, r5f21122dfp 02000 16 02fff 16 internal rom (data area) 1 note1: the data flash rom block a (2k bytes) and block b (2k bytes) are shown.
rev.0.10 oct 28, 2003 page 10 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) watchdog timer start register wdts xx 16 watchdog timer control register wdc 000xxxxx 2 processor mode register 0 pm0 xxxx0x00 2 system clock control register 0 cm0 01101000 2 system clock control register 1 cm1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register prcr 00xxx000 2 processor mode register 1 pm1 00xxx0x0 2 note 1: the blank areas are reserved and cannot be used by users. x : undefined oscillation stop detection register ocd 00000100 2 int0 input filter select register int0f xxxxx000 2 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register symbol after reset address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 watchdog timer reset register wdtr xx 16 4. special function register (sfr)
rev.0.10 oct 28, 2003 page 11 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) uart0 transmit interrupt control register s0tic xxxxx000 2 uart0 receive interrupt control register s0ric xxxxx000 2 uart1 transmit interrupt control register s1tic xxxxx000 2 uart1 receive interrupt control register s1ric xxxxx000 2 key input interrupt control register kupic xxxxx000 2 a-d conversion interrupt control register adic xxxxx000 2 int1 interrupt control register int1ic xxxxx000 2 int2 interrupt control register int2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int3 interrupt control register int3ic xxxxx000 2 note 1:the blank areas are reserved and cannot be used by users. x : undefined 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset timer x interrupt control register txic xxxxx000 2 timer y interrupt control register tyic xxxxx000 2 timer z interrupt control register tzic xxxxx000 2 timer c interrupt control register tcic xxxxx000 2
rev.0.10 oct 28, 2003 page 12 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 0089 16 008a 16 008b 16 008c 16 008d 16 008e 16 008f 16 0090 16 0091 16 0092 16 0093 16 0094 16 0095 16 0096 16 0097 16 0098 16 0099 16 009a 16 009b 16 009c 16 009d 16 009e 16 009f 16 00a0 16 00a1 16 00a2 16 00a3 16 00a4 16 00a5 16 00a6 16 00a7 16 00a8 16 00a9 16 00aa 16 00ab 16 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 00b1 16 00b2 16 00b3 16 00b4 16 00b5 16 00b6 16 00b7 16 00b8 16 00b9 16 00ba 16 00bb 16 00bc 16 00bd 16 00be 16 00bf 16 timer x register tx ff 16 timer y secondary tysc ff 16 external input enable register inten 00 16 prescaler y prey ff 16 uart0 transmit/receive mode register u0mr 00 16 uart0 transmit buffer register u0tb xx 16 xx 16 uart0 receive buffer register u0rb xx 16 xx 16 uart1 transmit/receive mode register u1mr 00 16 uart1 transmit buffer register u1tb xx 16 xx 16 uart1 receive buffer register u1rb xx 16 xx 16 uart0 bit rate generator u0brg xx 16 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart1 bit rate generator u1brg xx 16 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart transmit/receive control register 2 ucon 00 16 note : the blank areas are reserved and cannot be used by users. x : undefined address register symbol after reset timer y, z mode register tyzmr 00 16 timer y primary typr ff 16 timer y, z waveform output control register pum 00 16 prescaler z prez ff 16 timer z secondary tzsc ff 16 timer z primary tzpr ff 16 timer y, z output control register tyzoc 00 16 timer x mode register txmr 00 16 prescaler x prex ff 16 count source set register tcss 00 16 timer c register tc 00 16 00 16 key input enable register kien 00 16 timer c control register 0 tcc0 00 16 timer c control register 1 tcc1 00 16 capture register tm0 xx 16 xx 16
rev.0.10 oct 28, 2003 page 13 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c8 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 03fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 note 1: the blank areas are reserved and cannot be used by users. x : undefined a-d register ad xxxxxxxx 2 xxxxxxxx 2 a-d control register 0 adcon0 00000xxx 2 a-d control register 2 adcon2 00 16 a-d control register 1 adcon1 00 16 port p0 register p0 xx 16 port p0 direction register pd0 00 16 port p1 register p1 xx 16 port p1 direction register pd1 00 16 port p3 register p3 xx 16 port p3 direction register pd3 00 16 port p4 register p4 xx 16 port p4 direction register pd4 00 16 pull-up control register 0 pur0 00xx0000 2 port p1 drivability control register drr 00 16 register symbol after reset address pull-up control register 1 pur1 xxxxxx0x 2 flash memory control register 1 fmr1 1000000x 2 flash memory control register 0 fmr0 xx000001 2 flash memory control register 4 fmr4 0100000x 2
rev.0.10 oct 28, 2003 page 14 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics 5. electrical characteristics table 5.1 absolute maximum ratings operating ambient temperature parameter unit supply voltage output voltage v o p d power dissipation storage temperature rated value v v condition v cc t stg t opr symbol mw v cc =av cc v av cc v -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 (d version) c topr=25 c analog supply voltage v cc =av cc -0.3 to 6.5 v i input voltage -0.3 to v cc +0.3 -0.3 to v cc +0.3 c table 5.2 recommended operating conditions 2.7 5 . 5 t y p .m a x . u n i t p a r a m e t e r v c c 5.0 s u p p l y v o l t a g e s y m b o l min. standard a n a l o g s u p p l y v o l t a g e v cc a v c c v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h v s s a v s s 0.8v cc v v v c c 0 . 2 v c c " l " i n p u t v o l t a g e " h " i n p u t v o l t a g e v f (x in ) main clock input oscillation frequency v v i l 10 3.0v vcc 5.5v 2 . 7 v v c c < 3 . 0 v mhz m h z note 1: referenced to v cc = av cc = 2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. 2: the mean output current is the mean value within 100ms. 0 i o h ( s u m ) " h " p e a k a l l o u t p u t c u r r e n t s conditions s u m o f a l l p i n s ' i o h ( p e a k ) -60.0 ma i o h ( p e a k ) " h " p e a k o u t p u t c u r r e n t -10.0 ma i o h ( a v g ) " h " a v e r a g e o u t p u t c u r r e n t - 5 . 0m a i o l ( s u m ) " l " p e a k a l l o u t p u t c u r r e n t s s u m o f a l l p i n s ' i o l ( p e a k ) 60 ma i ol (peak) "l" peak output current except p1 0 to p1 7 p1 0 to p1 7 10 ma drive ability high d r i v e a b i l i t y l o w 30 10 ma m a i o l ( a v g ) " l " a v e r a g e o u t p u t c u r r e n t except p1 0 to p1 7 p1 0 to p1 7 d r i v e a b i l i t y h i g h drive ability low 5 1 5 5 m a m a ma 0 0 16
rev.0.10 oct 28, 2003 page 15 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics table 5.3 a-d conversion characteristics standard min. typ. max. resolution bit v ref =v cc 10 symbol parameter measuring condition unit lsb 3 r ladder t conv ladder resistance conversion time reference voltage analog input voltage v v ia v ref 0 2.0 v cc v ref note 1: referenced to v cc =av cc =2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. 2: when f ad is 10 mhz more, divide the f ad and make a-d operation clock frequency ( ad) lower than 10 mhz. 3: when the vcc is less than 4.2v, divide the f ad and make a-d operation clock frequency ( ad) lower than f ad /2. f(xin)= ad=10 mhz, vref=vcc=5.0v v ref =v cc absolute accuracy 10 bit mode 8 bit mode f(xin)= ad=10 mhz, vref=vcc=5.0v 2 lsb 10 bit mode 8 bit mode f(xin)= ad=10 mhz, vref=vcc=3.3v 5 lsb f(xin)= ad=10 mhz, vref=vcc=3.3v 2 lsb 10 40 k ? 10 bit mode 8 bit mode f(xin)= ad=10 mhz, vref=vcc=5.0v f(xin)= ad=10 mhz, vref=vcc=5.0v 3.3 2.8 s s v a-d operation clock frequency 2 without sample & hold with sample & hold 0.25 10 mhz 1.0 10 mhz figure 5.1 port p0 to p4 measurement circuit p0 p1 p2 p3 p4 30pf
rev.0.10 oct 28, 2003 page 16 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics table 5.4 flash memory (program area) electrical characteristics table 5.5 flash memory (data area block a, block b) electrical characteristics 4 figure 5.2 time delay from suspend request until erase suspend byte program time block erase time program, erase voltage read voltage 50 0.4 ? parameter standard min. typ. max unit measuring condition symbol program, erase temperature 2.7 2.7 0 5.5 5.5 60 s v v ? program/erase cycle 2 v cc = 5.0 v at topr = 25 ? 100 3 cycle v cc = 5.0 v at topr = 25 ? time delay from suspend request until erase suspend tbd ms t d(sr-es) b y t e p r o g r a m t i m e b l o c k e r a s e t i m e p r o g r a m , e r a s e v o l t a g e r e a d v o l t a g e 6 5 0.3 s p a r a m e t e r standard min. typ. max unit n o t e 1 : r e f e r e n c e d t o v c c = a v c c = 2 . 7 t o 5 . 5 v a t t o p r = 0 t o 6 0 c u n l e s s o t h e r w i s e s p e c i f i e d . 2 : d e f i n i t i o n o f p r o g r a m / e r a s e t h e c y c l e o f p r o g r a m / e r a s e s h o w s a c y c l e f o r e a c h b l o c k . i f t h e p r o g r a m / e r a s e n u m b e r i s n ( n = 1 0 0 , 1 0 0 0 0 ) , n t i m e s e r a s e c a n b e p e r f o r m e d f o r e a c h b l o c k . f o r e x a m p l e , i f p e r f o r m i n g o n e - b y t e w r i t e t o t h e d i s t i n c t a d d r e s s e s o n b l o c k a o f 2 k - b y t e b l o c k 2 0 4 8 t i m e s a n d t h e n e r a s i n g t h a t b l o c k , t h e n u m b e r o f p r o g r a m / e r a s e c y c l e s i s o n e t i m e . h o w e v e r , p e r f o r m i n g m u l t i p l e w r i t e s t o t h e s a m e a d d r e s s b e f o r e a n e r a s e o p e r a t i o n i s p r o h i b i t e d ( o v e r w r i t i n g p r o h i b i t e d ) . 3 : m a x i m u m n u m b e r s o f p r o g r a m / e r a s e c y c l e s f o r w h i c h a l l e l e c t r i c a l c h a r a c t e r i s t i c s i s g u a r a n t e e d . 4 : t a b l e 5 . 5 a p p l i e s f o r b l o c k a o r b w h e n t h e p r o g r a m / e r a s e c y c l e s a r e m o r e t h a n 1 0 0 0 . t h e b y t e p r o g r a m t i m e a n d b l o c k e r a s e t i m e u p t o 1 0 0 0 c y c l e s a r e t h e s a m e a s t h a t o f t h e p r o g r a m a r e a ( s e e t a b l e 5 . 4 ) . 5 : t o r e d u c e t h e n u m b e r o f p r o g r a m / e r a s e c y c l e s , a b l o c k e r a s e s h o u l d i d e a l l y b e p e r f o r m e d a f t e r w r i t i n g i n s e r i e s a s m a n y d i s t i n c t a d d r e s s e s ( o n l y o n e t i m e e a c h ) a s p o s s i b l e . i f p r o g r a m m i n g a s e t o f 1 6 b y t e s , w r i t e u p t o 1 2 8 s e t s a n d t h e n e r a s e t h e m o n e t i m e . t h i s w i l l r e s u l t i n i d e a l l y r e d u c i n g t h e n u m b e r o f p r o g r a m / e r a s e c y c l e s . a d d i t i o n a l l y , a v e r a g i n g t h e n u m b e r o f p r o g r a m / e r a s e c y c l e s f o r b l o c k a a n d b w i l l b e m o r e e f f e c t i v e . i t i s i m p o r t a n t t o t r a c k t h e t o t a l n u m b e r o f b l o c k e r a s e s a n d r e s t r i c t t h e n u m b e r . 6 : i f e r r o r o c c u r s d u r i n g b l o c k e r a s e , a t t e m p t t o e x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d , t h e n t h e b l o c k e r a s e c o m m a n d a t l e a s t t h r e e t i m e s u n t i l t h e e r a s e e r r o r d i s a p p e a r s . 7 : c u s t o m e r s d e s i r i n g p r o g r a m / e r a s e f a i l u r e r a t e i n f o r m a t i o n s h o u l d c o n t a c t t h e i r r e n e s a s t e c h n i c a l s u p p o r t r e p r e s e n t a - t i v e . 8 : 4 0 c f o r d v e r s i o n . measuring condition s y m b o l p r o g r a m , e r a s e t e m p e r a t u r e 2 . 7 2 . 7 2 0 8 5 . 5 5 . 5 8 5 s v v c pr o g r a m / e r a s e c y c l e 2 v c c = 5 . 0 v a t t o p r = 2 5 c 10000 3 c y c l e v c c = 5 . 0 v a t t o p r = 2 5 c t i m e d e l a y f r o m s u s p e n d r e q u e s t u n t i l e r a s e s u s p e n d t b d m s t d ( s r - e s ) fmr46 erase-suspend request (interrupt request) t d(sr-es)
rev.0.10 oct 28, 2003 page 17 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics table 5.7 electrical characteristics (1) [vcc=5v] symbol v oh v ol "l" output voltage "h" output voltage standard typ. unit measuring condition v v v min. max. v cc - 2.0 parameter i oh = - 5ma v hysteresis "h" input current i ih "l" input current i il v ram ram retention voltage v t+- v t- 0.2 v ? at stop mode 2.0 v i =5v v i =0v r fxin feedback resistance x in m ? r pullup pull-up resistance 167 k ? 30 125 note 1 : referenced to v cc =av cc =4.2 to 5.5v at topr = -20 to 85 ? / -40 to 85 ?, f(bclk)=20mhz unless otherwise specified. v cc except x out x out i oh = - 200a drive ability high drive ability low v cc - 0.3 v cc v i oh = - 1 ma v cc - 2.0 v cc - 2.0 i oh = - 500a v v v cc v cc p1 0 to p1 7 except x out p1 0 to p1 7 x out drive ability high drive ability low i oh = 5 ma i oh = 200 a i oh = 10 ma i oh = 5 ma 2.0 0.45 v 2.0 2.0 v drive ability high drive ability low i oh = 1 ma i oh =500a 2.0 2.0 v int o , int 1 , int 2 , int 3 , ki 0 , ki 1 , ki 2 , ki 3 , cntr 0 , cntr 1 , tc in , rxd 0 , rxd 1 reset 0.2 1.0 2.2 v v 5.0 - 5.0 ? v i =0v 50 1.0 f ring ring oscillator frequency 40 250 khz table 5.6 power circuit timing characteristics symbol standard typ. unit measuring condition min. max. parameter 2 note 1: the measureing condition is vcc=avcc=2.7 to 5.5 v and topr=25 c. 2: this shows the waiting time till the internal power supply generating circuit is stabilized during powering-on. 3: this shows the time till bclk starts from the interrupt acknowledgement to cancel stop mode. 150 td(r-s) stop release time 3 ms td(p-r) time for internal power supply stabilization during powering-on 2 ?
rev.0.10 oct 28, 2003 page 18 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics table 5.8 electrical characteristics (2) [vcc=5v] symbol standard typ. unit measuring condition min. max. parameter no division ma in single-chip mode, the output pins are open and other pins are v ss 8 14 x in =16 mhz (square wave) ma high-speed mode i cc power supply current (v cc =3.3 to 5.5v) note 1: the power supply current measuring is executed using the measuring program on frash memory. 2: timer y is operated with timer mode. wait mode a a a ma medium-speed mode ring oscillator mode wait mode ring oscillator on=125 khz x in =10 mhz (square wave) ring oscillator on=125 khz no division 5 x in =16 mhz (square wave) ring oscillator on=125 khz division by 8 3 x in =10 mhz (square wave) ring oscillator on=125 khz division by 8 2 ma main clock off ring oscillator on=125 khz ma main clock off ring oscillator on=125 khz peripheral clock operation tbd main clock off ring oscillator on=125 khz peripheral clock off stop mode main clock off ring oscillator off cm10="1" peripheral clock off 0.8 3.0 division by 8 0.4 when a wait instruction is executed 2 when a wait instruction is executed 2 2.0 tbd tbd tbd
rev.0.10 oct 28, 2003 page 19 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics timing requirements (unless otherwise noted: v cc = 5v, v ss = 0v at ta = 25 ?) [v cc =5v] table 5.9 x in input ________ table 5.10 cntr0 input, cntr1 input, int2 input ________ table 5.11 tcin input, int3 input table 5.12 serial i/o ________ table 5.13 external interrupt int0 input symbol t c (x in ) t wh (x in ) t wl (x in ) parameter x in input cycle time x in input high pulse width x in input low pulse width min. 62.5 30 30 max. unit ns ns ns standard parameter cntr0 input cycle time cntr0 input high pulse width cntr0 input low pulse width min. 100 40 40 max. unit ns ns ns standard symbol t c ( tcin ) t wh ( tcin ) t wl ( tcin ) parameter tcin input cycle time tcin input high pulse width tcin input low pulse width min. 400 1 200 2 200 2 max. unit ns ns ns standard note 1 : use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value. 2 : use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. symbol t c ( ck ) t w ( ckh ) t w ( ckl ) t d ( c-q ) t h ( c-q ) t su ( d-c ) t h ( c-d ) parameter clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time min. 200 100 100 0 35 90 max. unit ns ns ns ns ns ns ns standard 80 symbol t w ( inh ) t w ( inl ) parameter ________ int0 input high pulse width ________ int0 input low pulse width min. 250 1 250 2 max. unit ns ns standard note ________ ________ 1 : when the int0 input filter select bit selects the digital filter, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. ________ ________ 2 : when the int0 input filter select bit selects the digital filter, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. symbol t c ( cntr0 ) t wh ( cntr0 ) t wl ( cntr0 )
rev.0.10 oct 28, 2003 page 20 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics figure 5.3 vcc=5v timing diagram clk i txd i rxd i int i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 5v
rev.0.10 oct 28, 2003 page 21 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics table 5.14 electrical characteristics (3) [vcc=3v] symbol v oh v ol "l" output voltage "h" output voltage standard typ. unit measuring condition v v v min. max. v cc - 0.5 parameter i oh = - 1ma v hysteresis "h" input current i ih "l" input current i il v ram ram retention voltage v t+- v t- 0.2 v ? at stop mode 2.0 v i =3v r fxin feedback resistance x in m ? r pullup pull-up resistance k ? 66 125 note 1 : referenced to v cc =av cc =2.7 to 3.3v at topr = -20 to 85 ? / -40 to 85 ?, f(bclk)=10mhz unless otherwise specified. v cc except x out x out drive ability high drive ability low i oh = - 0.1 ma v cc - 0.5 v cc - 0.5 i oh = - 50 a v v v cc v cc p1 0 to p1 7 except x out p1 0 to p1 7 x out drive ability high drive ability low i oh = 1 ma i oh = 2 ma i oh = 1 ma 0.5 v 0.5 0.5 v drive ability high drive ability low i oh = 0.1 ma i oh =50 a 0.5 0.5 v int 0 , int 1 , int 2 , int 3 , ki 0 , ki 1 , ki 2 , ki 3 , cntro, cntr 1 , tc in , rxd 0 , rxd 1 reset 0.2 0.8 1.8 v 4.0 - 4.0 ? v i =0v 160 3.0 f ring ring oscillator frequency 40 250 khz v i =0v 500
rev.0.10 oct 28, 2003 page 22 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics table 5.15 electrical characteristics (4) [vcc=3v] symbol standard typ. unit measuring condition min. max. parameter no division ma in single-chip mode, the output pins are open and other pins are v ss 7 12 x in =16 mhz (square wave) ma high-speed mode i cc power supply current (v cc1 =2.7 to 3.3v) 0.4 note 1: the power supply current measuring is executed using the measuring program on frash memory. 2: timer y is operated with timer mode. wait mode a a a ma medium-speed mode ring oscillator mode wait mode ring oscillator on=125 khz x in =10 mhz (square wave) ring oscillator on=125 khz no division 5 x in =16 mhz (square wave) ring oscillator on=125 khz division by 8 2.5 x in =10 mhz (square wave) ring oscillator on=125 khz division by 8 1.6 ma main clock off ring oscillator on=125 khz division by 8 ma main clock off ring oscillator on=125 khz peripheral clock operation main clock off ring oscillator on=125 khz peripheral clock off stop mode main clock off ring oscillator off cm10="1" peripheral clock off 0.7 3.0 tbd when a wait instruction is executed 2 when a wait instruction is executed 2 2.0 tbd tbd tbd
rev.0.10 oct 28, 2003 page 23 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics timing requirements (unless otherwise noted: v cc = 3v, v ss = 0v at ta = 25 c) [v cc =3v] table 5.16 x in input ________ table 5.17 cntr0 input, cntr1 input, int2 input ________ table 5.18 tcin input, int3 input table 5.19 serial i/o ________ table 5.20 external interrupt int0 input symbol t c (x in ) t wh (x in ) t wl (x in ) parameter x in input cycle time x in input high pulse width x in input low pulse width min. 143 70 70 max. unit ns ns ns standard symbol t c ( cntr0 ) t wh ( cntr0 ) t wl ( cntr0 ) parameter cntr0 input cycle time cntr0 input high pulse width cntr0 input low pulse width min. 300 120 120 max. unit ns ns ns standard symbol t c ( tcin ) t wh ( tcin ) t wl ( tcin ) parameter tcin input cycle time tcin input high pulse width tcin input low pulse width min. 1200 1 600 2 600 2 max. unit ns ns ns standard symbol t c ( ck ) t w ( ckh ) t w ( ckl ) t d ( c-q ) t h ( c-q ) t su ( d-c ) t h ( c-d ) parameter clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time min. 300 150 150 0 55 90 max. unit ns ns ns ns ns ns ns standard 160 symbol t w ( inh ) t w ( inl ) parameter ________ int0 input high pulse width ________ int0 input low pulse width min. 380 1 380 2 max. unit ns ns standard note 1 : use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value. 2 : use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. note ________ ________ 1 : when the int0 input filter select bit selects the digital filter, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. ________ ________ 2 : when the int0 input filter select bit selects the digital filter, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
rev.0.10 oct 28, 2003 page 24 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics figure 5.4 vcc=3v timing diagram clk i txd i rxd i int i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 3v
rev.0.10 oct 28, 2003 page 25 of 25 r8c/12 group under development preliminary specification specifications in this manual are tentative and subject to change. package dimensions package dimensions lqfp32-p-0707-0.80 weight(g) jedec code eiaj package code lead material cu alloy 32p6u-a plastic 32pin 7 ? 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 i 2 1.0 m d m e 10 0 0.1 1.0 0.7 0.2 0.5 0.3 0.8 6.9 7.0 7.1 6.9 7.0 7.1 8.8 9.0 9.2 8.8 9.0 9.2 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e lp 0.45 0.6 0.5 7.4 7.4 0.25 0.75 x a3 recommended mount pad detail f a e h e h d d 1 8 24 17 25 32 16 9 m d b 2 m e e f e y b x m a 1 a 2 l l 1 lp a3 c i 2 mmp
revision history r8c/12 group data sheet rev. date description page summary a-1 0.10 oct 28, 2003 first edition issued
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